---------------------------------------------------------------------------------- -- Company: NOBOMI -- Engineer: Bohumil Novacek -- -- Create Date: 07/13/2012 -- Design Name: MZVGA -- Module Name: mzvga -- Project Name: mzvga -- Target Devices: 5M240ZT100C5N -- Tool versions: Quartus II 32-bit Programmer Version 12.0 -- Description: -- -- Dependencies: -- -- Revision: 1.0 -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mzvga is Port ( MZ_RGBI : in STD_LOGIC_VECTOR (3 downto 0); MZ_HSYNC : in STD_LOGIC; MZ_VSYNC : in STD_LOGIC; V_CLK : in STD_LOGIC; CLK80 : in STD_LOGIC; MZ_CLK : in STD_LOGIC; OUT_CLK : out STD_LOGIC; RAM_AD : out STD_LOGIC_VECTOR (17 downto 0); RAM_DT : inout STD_LOGIC_VECTOR (15 downto 0); RAM_WR : out STD_LOGIC; RAM_OE : out STD_LOGIC; VGA_RGB : out STD_LOGIC_VECTOR (5 downto 0); V_HSYNC : out STD_LOGIC; V_VSYNC : out STD_LOGIC; V_CLK_OUT : out STD_LOGIC); end mzvga; architecture RTL of mzvga is ----------------------------------------------------------------------------------------------------------------------- signal mzclk_div: std_logic_vector(9 downto 0); signal mzclkH: std_logic_vector(9 downto 0); signal mzclkV: std_logic_vector(8 downto 0); signal rMZ_HSYNC: std_logic; signal rrMZ_HSYNC: std_logic; signal r2MZ_HSYNC: std_logic; signal r3MZ_HSYNC: std_logic; --ochrana proti zakmitum signal vga_page: std_logic; signal mz_page: std_logic; signal tmp_page: std_logic; signal vga_h: std_logic_vector(10 downto 0); signal vga_v: std_logic_vector(9 downto 0); signal vga_h_tma: std_logic; signal vga_v_tma: std_logic; signal mz_rgbi_1: std_logic_vector(3 downto 0); signal mz_rgbi_2: std_logic_vector(3 downto 0); signal mz_rgbi_3: std_logic_vector(3 downto 0); signal mz_rgbi_all: std_logic_vector(15 downto 0); signal rd_buf: std_logic_vector(15 downto 0); signal vga_rgbi: std_logic_vector(3 downto 0); signal data_in_ready: std_logic; signal data_in_ready_set: std_logic; signal data_in_ready_reset: std_logic; signal v_clk_reg: std_logic; signal v_clk_neg: std_logic; signal v_clk_in: std_logic; begin process (MZ_HSYNC,rrMZ_HSYNC) begin if (MZ_HSYNC='0') then rMZ_HSYNC<='0'; elsif (rrMZ_HSYNC='1') then rMZ_HSYNC<='1'; end if; end process; process (data_in_ready_set,data_in_ready_reset) begin if (data_in_ready_set='1') then data_in_ready<='1'; elsif (data_in_ready_reset='1') then data_in_ready<='0'; end if; end process; process (v_clk_in) begin if v_clk_in'event and v_clk_in='0' then v_clk_reg <= v_clk_neg; ----------------------------------------------------------------------------------------------------------------------- --preddelic vytvari hodiny pro MZ-------------------------------------------------------------------------------------- r2MZ_HSYNC <= rMZ_HSYNC; OUT_CLK <= mzclk_div(9); if rMZ_HSYNC='0' and r2MZ_HSYNC='1' then mzclk_div <= "0010111010"; --lze nastavit offset cteni bitu else mzclk_div <= mzclk_div + 227; end if; ----------------------------------------------------------------------------------------------------------------------- end if; end process; v_clk_neg <= not v_clk_reg; v_clk_in <= V_CLK xor v_clk_neg; V_CLK_OUT <= v_clk_in; rrMZ_HSYNC <= not mzclkH(9); process (MZ_CLK) begin if MZ_CLK'event and MZ_CLK='0' then ----------------------------------------------------------------------------------------------------------------------- --nacitani obrazu a synchronizace s MZ--------------------------------------------------------------------------------- r3MZ_HSYNC <= rMZ_HSYNC; if rMZ_HSYNC='0' and r3MZ_HSYNC='1' then mzclkH <= "1011111001"; --horizontalni posuv (-260)+2-5 if MZ_VSYNC='0' then --naposledy na zacatky radku 2 mzclkV <= "111101000"; --vertikalni posuv 2-67+41 mz_page<=tmp_page; else mzclkV <= mzclkV + 1; if (mzclkV(8 downto 6)="001") then tmp_page<=not mz_page; end if; end if; else mzclkH <= mzclkH + 1; end if; case mzclkH(1 downto 0) is when "00" => mz_rgbi_1 <= MZ_RGBI; data_in_ready_set <= '1'; when "01" => mz_rgbi_2 <= MZ_RGBI; data_in_ready_set <= '0'; when "10" => mz_rgbi_3 <= MZ_RGBI; when others => mz_rgbi_all <= MZ_RGBI & mz_rgbi_3 & mz_rgbi_2 & mz_rgbi_1; --data_in_ready_set <= '1'; end case; ----------------------------------------------------------------------------------------------------------------------- end if; end process; process (V_CLK) begin if V_CLK'event and V_CLK='0' then ----------------------------------------------------------------------------------------------------------------------- --generovani vystupu SVGA---------------------------------------------------------------------------------------------- if vga_h=799+4 then --(1056-1)-256 vga_h<="11100000100"; vga_h_tma <= '1'; if vga_v=567-4 then vga_v_tma <= '1'; end if; if vga_v=569+16-1-2 then V_VSYNC<='1'; end if; if vga_v=573+16-1-2 then V_VSYNC<='0'; end if; if vga_v=627 then vga_page<=not tmp_page; vga_v<="0000000000"; vga_v_tma <= '0'; else vga_v <= vga_v + 1; end if; else vga_h <= vga_h + 1; end if; if vga_h=3 then vga_h_tma <= '0'; end if; if vga_h=1831+6-1 then V_HSYNC<='1'; end if; if vga_h=1959+6-1 then V_HSYNC<='0'; end if; case vga_h(1 downto 0) is when "10" => RAM_DT<="ZZZZZZZZZZZZZZZZ"; RAM_OE<='0'; when "11" => rd_buf<=RAM_DT; when "00" => RAM_OE<='1'; if (data_in_ready = '1') then --uloz RAM_DT<=mz_rgbi_all; data_in_ready_reset <= '1'; RAM_WR<='0'; end if; when others => RAM_WR<='1'; data_in_ready_reset <= '0'; end case; if ((vga_h_tma='1') or (vga_v_tma='1')) then vga_rgbi <= "0000"; else case vga_h(1 downto 0) is when "00" => vga_rgbi <= rd_buf(3 downto 0); when "01" => vga_rgbi <= rd_buf(7 downto 4); when "10" => vga_rgbi <= rd_buf(11 downto 8); when others => vga_rgbi <= rd_buf(15 downto 12); end case; end if; ----------------------------------------------------------------------------------------------------------------------- end if; end process; VGA_RGB(3 downto 0)<=vga_rgbi; VGA_RGB(4)<=vga_rgbi(3); VGA_RGB(5)<=vga_rgbi(3); RAM_AD<=mzclkH(9 downto 2) & mzclkV(8 downto 0) & mz_page when vga_h(1)='0' else vga_h(9 downto 2) & vga_v(9 downto 1) & vga_page; end RTL;